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ISA [clear filter]
Tuesday, September 15
 

10:35am CDT

The Open Power ISA: Architecture Compliancy and Future Foundations - Brian W. Thompto, IBM
The Open Power ISA enables access to unencumbered open innovation and a mature software ecosystem developed over the last 30 years.  In this talk, we will review the major options for architectural compliancy that provide freedom of choice in design, including four recently specified compliancy subsets, separate optional features, and custom extensions. IBM has also recently contributed the Power ISA Version 3.1 to the OpenPOWER Foundation. This latest architectural version includes a number of new features developed for the POWER10 server including a new foundation for future expansion via the introduction of an instruction prefix. New capabilities and compliancy implications will be summarized.

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Speakers
avatar for Brian W. Thompto

Brian W. Thompto

Distinguished Engineer, IBM
Brian W. Thompto is an IBM Distinguished Engineer based in Austin, TX. He is the chief core architect for IBM POWER servers and recently led the architecture and design of the processor core for POWER10, IBM's next generation server. He has over 20 years of experience leading global... Read More →


Tuesday September 15, 2020 10:35am - 11:05am CDT
Track 1

11:10am CDT

AI Acceleration Capabilities Using MMA(Matrix Multiply Assist) on POWER Architecture - Satish Kumar Sadasivam & Puneeth Bhat AH, IBM
Power ISA v3.01 has introduced a new set of architecture capabilities to accelerate matrix math operations called MMA (Matrix Multiply Assist). This will improve the performance of key compute kernels such as Matrix Multiplication, Convolution, Fourier Transform etc. which are fundamental building blocks for ML/DL workloads. This talk will introduce the audience to the POWER ISA MMA capabilities and detail the following: MMA’s architectural features, new instructions and lower/mixed precision data type support. The talk will cover programming a simple matrix multiplication function using MMA code and differentiate it from the traditional VSX (Vector Scalar Extension) based code sequence. The talk will delve into details of exploiting the full capability of MMA with assembly-level optimal code sequences for different data types. This talk will also cover compiler built-ins from GCC-10 and discuss exploitation of MMA capability in ML/DL frameworks using MMA-enabled OpenBLAS library.

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Speakers
avatar for Satish Kumar Sadasivam

Satish Kumar Sadasivam

Senior Performance Architect, Master Inventor, IBM
Satish Kumar Sadasivam is a Senior Performance Architect who leads the workload characterization and future architecture design space exploration team in IBM. He currently focuses on studying the low-level workload characteristics and exploring architectural and microarchitectural... Read More →
PB

Puneeth Bhat A H

Senior Performance Analyst, IBM
Puneeth Bhat A H is a Senior Performance Analyst working on the Power Systems Performance at IBM. Presently he is driving the cognitive workload and interpreter performance innovations for Power Processors. Puneeth, with 10 years of IBM experience, has expertise in the areas of processor... Read More →



Tuesday September 15, 2020 11:10am - 11:40am CDT
Track 1
  ISA
  • See Session Slides yes

12:45pm CDT

Towards a Formally-verified Software Toolchain for open ISAs - Boris Shingarov, LabWare
This talk summarizes lessons from several years of experimenting with automatic generation of compiler toolchains from processor description languages (PDL), using approaches ranging from superoptimization via logic programming to SMT-based binary analysis, and presents a new experimental system which builds on these lessons. The new approach takes ISA specifications written in the Sail PDL, as the starting point for software-tools synthesis and verification. Sail is used by practicing engineers to create full-scale formalizations of real ISAs; on the other hand, Sail is based on Lem and is mathematically rigorous. This talk demonstrates how the tool transforms a short sequence of POWER instructions into a proof of an invariant of the final state holding universally over the space of allowed behaviors.

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Speakers
avatar for Boris Shingarov

Boris Shingarov

Open-source VM designer, LabWare
Boris Shingarov designs open-source dynamic language VMs at LabWare. Currently Boris works on formal proof of correctness of JIT compilers, particularly for open-source ISAs. In the past, Boris has contributed to the creation of large-scale open-source software ecosystems through... Read More →


Tuesday September 15, 2020 12:45pm - 1:15pm CDT
Track 1

2:55pm CDT

Building Cache Coherent, Heterogeneous-ISA Processors Using P-Mesh - Jonathan Balkind, University of California, Santa Barbara
P-Mesh is the manycore cache coherence system underlying the OpenPiton research platform, which originally used the SPARCv9 ISA. A number of extensions to P-Mesh were needed to build the Bring Your Own Core (BYOC) platform, which added support for building heterogeneous-ISA processors made of cores of new, open ISAs like OpenPOWER. In this talk, Jonathan will introduce P-Mesh and the changes made to turn it into an ISA-agnostic memory system. Jonathan will detail the specific changes needed to support different ISAs, the new Transaction-Response Interface (TRI) for connecting cores, and initial efforts to support cores using the OpenPOWER ISA. Jonathan will also discuss efforts to connect multiple cores of different ISAs to build a single heterogeneous-ISA system.

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Speakers
avatar for Jonathan Balkind

Jonathan Balkind

Assistant Professor, University of California, Santa Barbara
Jonathan Balkind is an Assistant Professor in the Department of Computer Science at the University of California, Santa Barbara. His research interests lie at the intersection of Computer Architecture, Programming Languages, and Operating Systems. He is the Lead Architect of OpenPiton... Read More →



Tuesday September 15, 2020 2:55pm - 3:25pm CDT
Track 1
  Cores  ISA
  • See Session Slides yes
 
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