OpenPOWER Summit North America 2020

POWER10 is IBM's next generation POWER micro-processor focused on enterprise computing. This talk will describe many of the new innovations and capabilities of POWER10 that build upon the strengths of recent generations and provide flexibility for the enterprise cloud.  POWER10 is fabricated using Samsung 7nm technology. It features a new core microarchitecture focused on energy efficiency, thread strength, increased SIMD execution capabilities, and instruction set enhancements targeted toward AI optimization. It also provides a substantial data plane bandwidth increase coupled with next generation OpenCAPI accelerator attach and Open Memory Interface (OMI) capabilities. A modular packaging architecture enables a broad range of deployments optimized for socket throughput, thread strength, cost, and scale. The PowerAXON high bandwidth, low latency, multi-protocol link architecture combines with numerous scaling architecture enhancements to provide robust large system characteristics and with scale-out system architectures to provide disaggregated memory clustering capabilities.

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The market tested A2I POWER processor core RTL and associated FPGA implementation were recently open sourced in June 2020.  This presentation will describe the utility of the AXI bus as a key enabler for low-cost edge of network solutions. In addition, a practical approach to current ISA compliance will be described as well as the benefits of the released FPGA capabilities as a suitable starting point for 3rd party engagement.

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An out of order, single thread optimized core derived from the highly scalable in order commercially proven A2I core will be described.  The design leverages the same tightly coupled AXU accelerator interface as A2I.  An overview of key microarchitecture and features and a brief description of cost/power benefits when implemented in the 7nm technology will be offered.  Finally, a description of the associated FPGA environment and simple how to video will be shown.

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P-Mesh is the manycore cache coherence system underlying the OpenPiton research platform, which originally used the SPARCv9 ISA. A number of extensions to P-Mesh were needed to build the Bring Your Own Core (BYOC) platform, which added support for building heterogeneous-ISA processors made of cores of new, open ISAs like OpenPOWER. In this talk, Jonathan will introduce P-Mesh and the changes made to turn it into an ISA-agnostic memory system. Jonathan will detail the specific changes needed to support different ISAs, the new Transaction-Response Interface (TRI) for connecting cores, and initial efforts to support cores using the OpenPOWER ISA. Jonathan will also discuss efforts to connect multiple cores of different ISAs to build a single heterogeneous-ISA system.

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Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux.

From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs.

This presentation will give an overview of the Microwatt core. It will also include an overview of GHDL and how it can be used for both simulation and synthesis of a medium complexity VHDL project.

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LibreSOC is a hybrid CPU, VPU and GPU that is to be free of DRM and spying backdoor coprocessors, and to be libre licensed to the bedrock. To engender business and end-user trust the design is being developed fully transparently following best Libre Development practices, aims for full coverage with Formal Correctness Proofs, first class documentation suitable for both educational engagement as well as customer and developer support, and to act as a Reference and experimental Platform for exploration of advanced 3D and Video extensions to the Power ISA, under the guidance and mentorship of the OpenPOWER Foundation. With EUR 350,000 funding from NLNet under their Privacy and Enhanced Trust Programme, LibreSOC's first target is a 180nm test ASIC, as a first step on a roadmap that includes a Quad Core SoC suitable for use in tablets, netbooks and the SBC Industrial markets.